| 摘要 |
PURPOSE: To provide a synchronous type semiconductor memory in which an input buffer circuit can be activated only by a required operation cycle without deteriorating high speed responsiveness of an input buffer, and reduction of the current consumption can be realized. CONSTITUTION: Since the combination of control signals (Control) such as/CS, /RAS, /CAS, /WE makes only a command cycle requiring input from address pins of an active command (ACTV), a read-command (READ, READA), a write- command (WRITE, WRITEA), a mode register command (MRS), a pre-charge command (PRE) or the like dynamically perform latch operation, when an iRAS signal is in a low level at a rising edge of an iCLK signal (Fig.7), or when the iRAS signal or an iCAS signal is in a low level at a rising edge of the iCLK signal (Fig.9) a latch signal aCLK is outputted and address Add or the like are latched.
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