| 发明名称 |
High speed data processor for XDSL data transmission, has directly addressable input and output intermediate interface memories |
| 摘要 |
A data memory (20) is connected with a RISC data processing unit (13) containing several addressable registers. The input intermediate interface memories (9) and the output intermediate interface memories (26) are directly addressable through an interface address bus (24) by the data processing unit.
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| 申请公布号 |
DE10040389(A1) |
申请公布日期 |
2002.03.07 |
| 申请号 |
DE20001040389 |
申请日期 |
2000.08.18 |
| 申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
NIE, XIAONING;MAYR, CLAUDIA |
| 分类号 |
H04Q11/04;(IPC1-7):G06F13/16;G06F3/05;G06F12/08 |
主分类号 |
H04Q11/04 |
| 代理机构 |
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