发明名称 Integrated circuit defect review and classification process
摘要 The present invention relates to circuit defect detection, classification, and review in the wafer stage of the integrated circuit semiconductor device manufacturing process. The method of processing integrated circuit semiconductor dice on a wafer in a manufacturing process for dice comprises the steps of visually inspecting the dice on the wafer to determine defects thereon, summarizing the number, types, and ranges of sizes of the defects of the dice on the wafer, and determining if the wafer is acceptable to proceed in the manufacturing process.
申请公布号 US2002024661(A1) 申请公布日期 2002.02.28
申请号 US20010941253 申请日期 2001.08.28
申请人 ZEIMANTZ LISA R. 发明人 ZEIMANTZ LISA R.
分类号 G01N21/95;G01Q30/02;(IPC1-7):G01N21/00 主分类号 G01N21/95
代理机构 代理人
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