发明名称 |
DIGITAL KEY TELEPHONE SET AND DIGITAL KEY TELEPHONE SYSTEM |
摘要 |
A clock generating circuit generates a clock of a rate corresponding to a Dch rate in response to a specification from the exterior. A counting circuit detects completion of reception of one frame by counting the clock number up to "11" at timing at which a start bit detecting circuit detects a start bit in a serial signal. An S/P converting circuit fetches a serial Dch signal bit by bit in synchronism with the clock, outputs the latest fetched 10 bits in a parallel form and latches eight bits of a real data portion among the output data into a latch circuit at the time when reception of one frame is completed. In parallel with the above operation, a parity calculating circuit and flag/interruption generating circuit set various flags and generate a reception completion interruption.
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申请公布号 |
CA2356091(A1) |
申请公布日期 |
2002.02.28 |
申请号 |
CA20012356091 |
申请日期 |
2001.08.29 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
TAKAHASHI, TOSHIAKI;TANAKA, TOSHIAKI;HORIUCHI, TAKESHI |
分类号 |
H04L5/16;H04L7/04;H04M1/00;H04M9/00;H04Q3/58;(IPC1-7):H04M11/06 |
主分类号 |
H04L5/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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