发明名称 Linear half-rate phase detector and clock and data recovery circuit
摘要 Method and apparatus for recovering a clock and data from a data signal. One method of the invention includes receiving the data signal having a first data rate, receiving the clock signal having a first clock frequency, alternating between a first level and a second level, wherein the first data rate is twice the first clock frequency. A first signal is generated by passing the data signal when the clock signal is at the first level, and storing the data signal when the clock signal is at the second level. A second signal is generated by passing the data signal when the clock signal is at the second level, and storing the data signal when the clock signal is at the first level. A third signal is generated by passing the first signal when the clock signal is at the second level, and storing the first signal when the clock signal is at the first level. A fourth signal is generated by passing the second signal when the clock signal is at the first level, and storing the second signal when the clock signal is at the second level. An error signal is generated by taking the exclusive-OR of the first signal and the second signal, and a reference signal is generated by taking the exclusive-OR of the third signal and the fourth signal.
申请公布号 US2002021470(A1) 申请公布日期 2002.02.21
申请号 US20010782687 申请日期 2001.02.12
申请人 SAVOJ JAFAR 发明人 SAVOJ JAFAR
分类号 G01R25/00;H03D13/00;H03K3/03;H03L7/089;H03L7/091;H03L7/099;H04L7/033;(IPC1-7):H04B10/00 主分类号 G01R25/00
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