| 摘要 |
The present invention provides an architecture for a core logic unit including an embedded graphics controller. This architecture facilitates high-bandwidth communications between the graphics controller and other computer system components, such as the processor and the system memory. Thus, one embodiment of the present invention provides a core logic unit within a computer system including a processor interface for communicating with a processor, a memory interface for communicating with a system memory, and a bus interface for communicating across a computer system bus. It also includes a switch, coupled to the processor interface, the memory interface and the bus interface, for facilitating data transfers between these interfaces. The switch is connected to a graphics controller, which is located on the same semiconductor chip as the switch, for performing computations for displaying images on a computer system display. A variation of the above embodiment includes a Graphics Address Relocation Table (GART), which performs address translations on-the-fly for addresses crossing the switch that fall within the reserved range of addresses, and does not perform translations for other addresses. These address translations map addresses from the reserved range of graphics addresses to locations in system memory which contain graphics data. In another variation, the graphics controller is coupled to the switch through both a processor port, for communicating with a processor, and a separate memory port, for communicating with the system memory. The processor port and the memory port are each connected to the switch through separate read and write paths.
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