| 摘要 |
<p>PROBLEM TO BE SOLVED: To sufficiently utilize a high speed circuit to improve the throughput of a system by flexibly coping with changes of delay time due to changes of conditions such as kinds of high speed memories and high speed input/output circuits to be connected outside, boards to be mounted. SOLUTION: An external clock Extclk based on a system clock Sysclk is provided to the circuit to be controlled, data Data from the circuit to be controlled is fetched through a data interface circuit 2, the data Data is fetched in a data latch 4(1) consisting of plural stages to which clocks Clock1, to Clock(n) selected from among outputs of multi-phase PLL 8 to generate clocks with plural phases by a selector 9 are supplied and a signal in the optimal timing to be fetched in a data latch 6 to be operated by the system clock Sysclk is selected from among plural pieces of output data Data1 to Data(n) in the data latch 4(1) and raw data Data by a data selector 5.</p> |
