发明名称 VERIFICATION SYSTEM AND EMULATION BOARD
摘要 PROBLEM TO BE SOLVED: To provide a reusable verification system to reduce preparation period and cost. SOLUTION: In the verification system to verify a master board control LSI 4 to input/output data to a processor and a slave board control LSI 6 to process the inputted data and to output its result to the master board control LSI 4, a pseudo processor circuit 13 to accept input of the data, to output the data to the master board control LSI 4 as data from the processor, to simultaneously acquire and output the data to be outputted by the master board control LSI 4 as the data to be outputted to the processor is provided, the master board control LSI 4 is provided with a CPU I/F circuit 7 to control input/output of the data with the pseudo processor circuit 13 and a communication I/F circuit 8 between master and slave to control the input/output of the data with the slave board control LSI 6 and the slave board control LSI 6 is provided with a communication I/F circuit 17 between slave and master to control the input/ output of the data with the master board control LSI 4.
申请公布号 JP2002041321(A) 申请公布日期 2002.02.08
申请号 JP20000221870 申请日期 2000.07.24
申请人 MITSUBISHI ELECTRIC CORP 发明人 HORIKOSHI MIKA
分类号 G06F17/50;G06F11/22 主分类号 G06F17/50
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