发明名称 |
Semiconductor device and method of manufacturing the same |
摘要 |
A sidewall oxide layer and a sidewall insulation layer are formed to cover the edge portion of an SOI layer. A channel stopper region is formed in the vicinity of the edge portion of the SOI layer. A protruded insulation layer is formed on the channel stopper region. A gate electrode extends from a region over the SOI layer to the protruded insulation layer and the sidewall insulation layer. In this way, reduction in threshold voltage Vth of a parasitic MOS transistor at the edge portion of the SOI layer can be suppressed.
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申请公布号 |
US2002016025(A1) |
申请公布日期 |
2002.02.07 |
申请号 |
US20000481385 |
申请日期 |
2000.01.12 |
申请人 |
IPPOSHI TAKASHI;IWAMATSU TOSHIAKI;YAMAGUCHI YASUO |
发明人 |
IPPOSHI TAKASHI;IWAMATSU TOSHIAKI;YAMAGUCHI YASUO |
分类号 |
H01L21/76;H01L21/336;H01L21/762;H01L27/12;H01L29/06;H01L29/786;(IPC1-7):H01L21/00;H01L21/84 |
主分类号 |
H01L21/76 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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