| 摘要 |
A CPU (1) outputs a data signal (DI) in synchronization with an internal clock signal (Iclk). A device (101), which is an integrated circuit, is connected with a delay circuit (10) which is placed outside the device (101). The delay circuit (10) delays the internal clock signal (Iclk) for a delay time shorter than one cycle thereof, and thereby supplies the delayed signal as a delay clock signal (Dclk) to the device (101). A data transfer control circuit (2) delays the data signal (DI) for the delay time of the delay clock signal (Dclk) according to the delay clock signal (Dclk) and a control signal (CS) outputted by the CPU (1), and outputs the delayed data signal as a data signal (DE) to an external device. Since the external device operates in accordance with a control signal (WR) outputted synchronously with the internal clock signal (Iclk), a hold time corresponding to the delay time can be ensured. Thus, an external device, which requires a long hold time, is connectable with the device (101).
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