发明名称 Failure analysis method for chip of ball grid array type semiconductor
摘要 In a failure analysis method for a ball grid array type semiconductor device comprising a semiconductor chip having pads, first solder balls, an interposer substrate and second solder balls, the second solder balls and the interposer substrate are removed from the semiconductor device, and then, the first solder balls are removed from the semiconductor device. Then, the semiconductor device is mounted on a package, and a wire bonding operation is performed between the pads of the semiconductor chip and bonding pads of the package. Finally, a test operation is performed upon the semiconductor chip by mounting the package on a tester.
申请公布号 US2002013009(A1) 申请公布日期 2002.01.31
申请号 US20010822368 申请日期 2001.04.02
申请人 NEC CORPORATION 发明人 OZAWA TADASHI
分类号 G01R31/26;G01R1/073;H01L21/60;(IPC1-7):H01L21/66;H01L21/44;H01L21/48;H01L21/50 主分类号 G01R31/26
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