SEMICONDUCTOR MEMORY AND CONTROL METHOD

摘要

A semiconductor memory in which no operating current caused by the noise of an address signal fed from outside is effectively suppressed without retarding the operating speed during read/write. The semiconductor memory comprises a circuit system including a filter circuit (102) for removing the noise of an address signal fed from outside and an ATD circuit (311) for detecting a transition of the address signal before it passes through the filter circuit (102) and generating a first address transition detection signal ( phi ATD1) if a transition is detected and a circuit system including an ATD circuit (321) for detecting a transition of the address signal after it passes the filter circuit (102) and generating a second address transition detection signal ( phi ATD2) if a transition is detected. The refresh is controlled by the first address transition detection signal ( phi ATD1), and the read/write is controlled by the second address transition detection signal ( phi ATD2). Thus if noise is generated, only refresh is carried out, and the operating current is effectively suppressed. A method for controlling such a semiconductor memory is also disclosed.