SEMICONDUCTOR INTEGRATED CIRCUIT CAPABLE OF BOUNDARY SCAN TEST

摘要

PROBLEM TO BE SOLVED: To enable a normal board test of a semiconductor integrated circuit having output signals reduced to operate simultaneously by an output signal simultaneous operation measures by forming a boundary scan test pattern without taking the simultaneous operation measures into consideration. SOLUTION: This semiconductor integrated circuit 100 is designed to reduce the number of simultaneous operations of output signals and is provided with a boundary scan test circuit. A delay element DL is set for at least one register 104i of a plurality of boundary scan registers to a signal path Bi which passes test signals without passing normal signals in the boundary scan register.