| 摘要 |
A method of generating a test pattern for a semiconductor integrated circuit comprising a logic circuit containing a combinational logic element, a first sequential circuit having an output side connected to an input side of the logic circuit, and a second sequential circuit having an input side connected to an output side of the logic circuit, whereby a test pattern for testing a signal path between the first and second sequential circuits for a data retention error associated with data held by the second sequential circuit based on output data of the second sequential circuit is generated. To generate the test pattern, a first test pattern is generated by setting, at the first sequential circuit, a first set value for the signal path such that the signal path is activated immediately before and after one pulse of a clock signal for synchronization is inputted and a second test pattern is generated by setting, at the first sequential circuit, a second set value obtained by inverting the first set value.
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