Integrated circuit packaging structure

摘要

An plural integrated memory circuit structure which can accommodate two or four memory chips 2c and 2e in an aperture formed in an upper circuit board 3a mounted upon a lower circuit board 4a, with connecting wires 6a protected by encapsulation 5a and 5b. The packaging structure has circuitry which forms independent data buses for each memory chip while implementing the address buses and control buses in parallel. Two memory chips may be mounted adjacent and four may be mounted adjacent and stacked (as depicted). Stacked memory chips may be mounted back to back by an adhesive tape.