发明名称 Display control circuit and display control method
摘要 A display control circuit of the present invention includes: a clock generator for generating a first clock signal having a single frequency; a frequency divider for dividing the frequency of the first clock signal generated by the clock generator, thereby providing a second clock signal; a selection signal generation section for generating a selection signal upon which one of a binary display mode and a gray-scale display mode is selected; a selector for selecting one of the first clock signal and the second clock signal based on the selection signal; and a display circuit for performing one of the binary display mode and the gray-scale display mode using the selected clock signal.
申请公布号 US6339422(B1) 申请公布日期 2002.01.15
申请号 US19980181243 申请日期 1998.10.28
申请人 SHARP KABUSHIKI KAISHA 发明人 KUWAJIMA HIDENORI;MATSUMOTO TOSHIO
分类号 G02F1/133;G09G3/20;G09G3/36;G09G5/18;G09G5/399;(IPC1-7):G09G5/00 主分类号 G02F1/133
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