| 摘要 |
PROBLEM TO BE SOLVED: To evaluate accurately and efficiently an access time of a memory core incorporated in a semiconductor integrated circuit device. SOLUTION: An external clock signal EXT-CLK is transmitted to a memory core 50 as a clock signal CLK through first signal transmitting paths 34, 35. The memory core 50 starts read-out operation responding to the activation of the clock signal CLK. Read-out data Qn outputted from the memory core 50 is latched by a latch circuit 70. An external signal EXT-LAT indicating latch timing is transmitted to the latch circuit 70 as a latch timing signal LAT through second signal transmitting paths 44, 45. Signal delay by the first and the second signal transmitting paths are made the same by arranging delay circuits 80, 85 on at least one side of the first and the second signal transmitting paths.
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