发明名称 INFORMATION MULTIPLEX TRANSMISSION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide an information multiplex transmission circuit capable of storing pieces of transmission information in a single memory, sending the stored information and flexibly increasing/decreasing transmission information length and the number of the pieces of transmission information. SOLUTION: This information multiplex transmission circuit is provided with: a memory for string input data and repeated instruction data; and a FIFO for storing the addresses of the memory and the leading addresses of information stored in the memory; a NAND circuit for inverting the logical level of AND of an RE signal and a WE signal stored in the memory; an adder for adding the output from the NAND circuit and the output from the FIFO; a delay flip flop for storing the output of the adder; a selector for selecting one of the outputs of the adder and the delay flip flop; and an OR circuit for executing the OR operation of a recording start signal, a recording stop signal, a leasing address updating signal, and the repeated instruction data outputted from the memory and supplying the OR operation result to the selector as a selection signal.
申请公布号 JP2002009952(A) 申请公布日期 2002.01.11
申请号 JP20000187610 申请日期 2000.06.22
申请人 FUJITSU LTD 发明人 MIYAMOTO HIROAKI;YAMADA HIDEAKI;ISHII MASAYUKI;OTONARI SHOEI
分类号 G10L19/00;H04J3/00;H04M3/487;(IPC1-7):H04M3/487 主分类号 G10L19/00
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