| 摘要 |
A display parameter synchronous holding circuit 20 comprises a register group 21 for receiving display parameters DP separated by variable length decoding circuit, a selector 24 for selecting and outputting either the display parameters DP or the output of the register group 21, register group 22 for receiving the output of the selector 24, a register group 23 for storing the output of the register group 22 in response to VSYNC, and a control circuit 25 for causing the selector 24 to select the output of the register group 21 and making latch signals SH2 and SH1 to register groups 22 and 21 active in the order when the picture coding type PCT indicates I-picture or P-picture, and for causing the selector 24 to select DP and making SH2 active when PCT indicates B-picture.
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