REFERENCE VOLTAGE STABILIZATION CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE: A reference voltage stabilization circuit of a semiconductor memory device is provided, which generates a stable reference voltage without being unstable by a junction capacitor or a coupling capacitor in a high frequency. CONSTITUTION: The first NMOS transistor(200) receives a voltage activating an NMOS transistor through a gate terminal and receives a reference voltage(Vref) through a source terminal. A capacitor(210) is connected to a drain of the first NMOS transistor. And the second NMOS transistor(220) receives a voltage activating an NMOS transistor through a gate terminal and its source-drain path is formed between the capacitor and a ground terminal(qvss). The first and the second NMOS transistor are always activated and act as resistors between a reference voltage applying terminal and the capacitor or between the capacitor and the ground terminal. The NMOS transistors prevent a noise due to a bouncing at the ground terminal from being transferred to the reference voltage. The capacitor stabilizes a level of the reference voltage.