发明名称 |
Multi-processor system verification circuitry |
摘要 |
A multiprocessor system (40) includes a MPU subsystem (12), with master MPU (16) and shared memory (24), and a DSP/Coprocessor subsystem (14), with one or more slave DSP/Coprocessors (26). The system memory (20) is accessed by each DSP/Coprocessor subsystem (14) through a cache (28) and external memory interface (30). A verification interface (42) is used in verification mode to isolate the DSP/Coprocessor subsystem (14) from the MPU subsystem (12) and to translate system memory requests from the external memory interfaces (30) (through an arbiter (52), where multiple external memory interfaces are used) to a protocol which can be used to access the data from the shared memory (24).
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申请公布号 |
US2002004823(A1) |
申请公布日期 |
2002.01.10 |
申请号 |
US20010778495 |
申请日期 |
2001.02.07 |
申请人 |
ANDERSON MARQUETTE JOHN;BEDERR HAKIM |
发明人 |
ANDERSON MARQUETTE JOHN;BEDERR HAKIM |
分类号 |
G06F11/267;G06F11/27;(IPC1-7):G06F15/16 |
主分类号 |
G06F11/267 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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