| 摘要 |
PURPOSE: A latch circuit of a semiconductor memory device is provided, which increases a margin of a setup time and a hold time by reducing latency and widening window of the setup time and the hold time until data is output from a clock. CONSTITUTION: A precharge transistor(300) precharges a node A by receiving a clock(CLK), and an input part(310) receives the clock and data and an output of a delay part(330). The first latch stage(320) latches the node A, and the delay part delays the clock and a signal of the node A. An output part(340) outputs an output signal(Output) by receiving the signal of the node A and the clock. And the second latch stage(350) latches the above output signal. The precharge transistor receives the clock through a gate and comprises a PMOS transistor where a source-drain path is connected between a power supply voltage stage and the node A. And the input part comprises three NMOS transistors(311,312,313), and the delay part comprises an NAND gate(331) receiving the clock and the signal of the node A and the first inverter(332) receiving an output signal of the NAND gate and the second inverter(333) receiving an output of the first inverter. And the output part comprises one PMOS transistor(341) and two NMOS transistors(342,343).
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