发明名称 |
Semiconductor memory device |
摘要 |
In a clock synchronous memory like a double data rate synchronous DRAM, a register is provided which is capable of setting a value (advanced latency) for specifying an input or entry cycle for a read or write command. Further, a timing adjustment register (124, 125) for delaying a signal by a predetermined cycle time according to the advanced latency set to the register is provided on a signal path in a column address system, which is formed between a column address latch circuit (110) and a column decoder (116).
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申请公布号 |
US2002003747(A1) |
申请公布日期 |
2002.01.10 |
申请号 |
US20010871911 |
申请日期 |
2001.06.04 |
申请人 |
YAHATA HIDEHARU;HORIGUCHI MASASHI;FUJISAWA HIROKI;TAKAHASHI TSUGIO;NAKAMURA MASAYUKI |
发明人 |
YAHATA HIDEHARU;HORIGUCHI MASASHI;FUJISAWA HIROKI;TAKAHASHI TSUGIO;NAKAMURA MASAYUKI |
分类号 |
G11C11/407;G11C7/10;G11C7/22;G11C8/18;G11C11/4063;G11C11/4076;G11C11/408;G11C29/04;(IPC1-7):G11C8/00 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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