| 摘要 |
A circuit synchronizes row and column access operations in a semiconductor memory having an array of bit lines pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers. The circui t comprises a word line timing pulse for activating of at least one of the word lines, a first delay circuit coupled with the word line timing pulse for delaying the word line timing pulse by a first predetermined time, and a first logic circuit for logically combining the wo rd line timing pulse and the word line timing pulse delayed by the first delay circuit. The output of the first logic circuit provides a sense amplifier enable signal for enabling th e sense amplifier power supply circuit. The circuit further comprises a second delay circuit coupled with the word line timing pulse for delaying the word line timing pulse by a seco nd predetermined time. The circuit yet further comprises a second logic circuit for logically combining the word line timing pulse and the word line timing pulse delayed by the second delay circuit for providing a column select enable signal. The column select enable signal enables selected ones of a plurality of column access devices, which are activated a predetermined time period after the sense amplifier power supply circuit is enabled.
|
