| 摘要 |
PURPOSE: Integrated memory having memory cells with magnetoresistive memory effect is provided to reduce outlay for repairing the memory in the event of a defect of a memory cell which triggers a short between a row line and a column line. CONSTITUTION: Any known GMR/TMR elements are suitable as the memory cells, provided they exhibit higher impedance than the column lines (BL0 - BLn) and the row lines( WL0 - WLm)). The memory here comprises an exemplary number of word lines and bit lines. The memory cells MC, which are arranged in a matrix-type memory cell field(1), are each wired between one of the bit lines BL0 to BLn and one of the word lines(WL0 - WLm).
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