| 摘要 |
A contactless, nonvolatile metal oxide semiconductor memory device having a rectangular array of memory cells interconnected by word-lines in the row direction of the array and bit-lines in the column direction of the array. Each memory cell has a structurally asymmetrical pair of floating gate, MOS field effect transistors of the same row that share a common source region (bit line) within a semiconductor substrate. The asymmetry of the structure of the floating gates of the two transistors enables programming/reading and monitoring of the cell to be effected simultaneously. The structure of the floating gate is also responsible for a relatively large capacitive coupling between the floating gates and the control gate (word line) which lies above them. Since the floating gates essentially serve as a mask for implantation of program/read and monitor drain regions within the substrate, fabrication of the device incorporates self-aligning process steps.
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