发明名称 DISPLAY CIRCUIT
摘要 PURPOSE: To provide the circuit for performing rotated or enlarged/reduced display synchronously with dots, lines or frames without reloading the contents of a display memory concerning the display circuit for displaying bit map image data, which are plotted on an image memory, on a display device. CONSTITUTION: An arithmetic and logic unit 1 calculates the address of a display memory 2 by inputting address counter outputs and timing signals and performing multiplication during a horizontal or vertical flyback, time and cumulative addition for each dot and line. Thus, a smoothly rotated moving image or the like can be displayed by performing the multiplication once a display frame or a display line and the cumulative addition for each dot or once a display line without performing highspeed arithmetic for each dot clock. Since even a multiplier at low speed is avilable and the time sharing operation of the multiplier is enabled, circuit scale is reduced and the circuit can be manufactured at low cost.
申请公布号 KR100320483(B1) 申请公布日期 2001.12.28
申请号 KR19930010587 申请日期 1993.06.11
申请人 SEIKO EPSON CORPORATION 发明人 INOUE KAZUAKI
分类号 G06F3/153;G06T3/00;G09G5/00;G09G5/12;G09G5/18;G09G5/36;G09G5/39;H04N5/262;(IPC1-7):G09G5/36 主分类号 G06F3/153
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