APPARATUS AND METHOD FOR ISSUE GROUPING OF INSTRUCTIONS IN A VLIW PROCESSOR

摘要

An apparatus and method for issue grouping of instructions (204-216) in a VLIW processor is disclosed. There can be up to three issue groups in each VLIW packet (200). Template (202) in the VLIW packet (200) comprises two 3-bit, issue group end markers (224, 226) identifying the last instruction of issue group 1 and issue group 2, respectively. Any instructions in the VLIW packet falling outside the first two groups are placed in a third issue group. The template (202) further comprises a chaining bit (228) used to chain instructions appearing after the last instruction of the last issue group of a first VLIW packet to the instructions in the first issue group of a second VLIW packet. Mask generation logic (612) along with other logic blocks (608, 610, 614, 616) are utilized to generate a mask to pass through instructions in a VLIW packet (600) which belong to a same issue group for execution in a same clock cycle.