发明名称 Semiconductor circuit with adjustment of double data rate data latch timings
摘要 A semiconductor circuit which receives a strobe signal and a data signal includes a latch-signal-generation circuit which generates a first latch signal delayed by a first delay time relative to the strobe signal and a second latch signal inverted and delayed by a second delay time relative to the strobe signal, a control circuit which adaptively controls the latch-signal-generation circuit to adjust timings of the first and second latch signals such that the first delay time and the second delay time become substantially equal, and a latch circuit which latches the data signal at edge timings of the first and second latch signals.
申请公布号 US6333875(B1) 申请公布日期 2001.12.25
申请号 US20000666586 申请日期 2000.09.20
申请人 FUJITSU LIMITED 发明人 SHINOZAKI NAOHARU
分类号 G11C11/407;G11C7/10;G11C11/4076;G11C11/4093;H03K3/356;H03K19/0175;(IPC1-7):G11C7/00 主分类号 G11C11/407
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