发明名称 |
Method of generating test patterns for a logic circuit, a system performing the method, and a computer readable medium instructing the system to perform the method |
摘要 |
In a method of test pattern generation for logic circuits, a whole circuit is divided into a plurality of partial circuits for test pattern generation by distributed-processing. ATG (Algorithmic Test Generation) process is performed per each of the partial circuits based on the result of RTG (Random Test Generation) process. Also disclosed are a test pattern generation system performing the method, and computer readable media having program for the test pattern generation system to perform the method.
|
申请公布号 |
US6334199(B1) |
申请公布日期 |
2001.12.25 |
申请号 |
US19990236903 |
申请日期 |
1999.01.26 |
申请人 |
NEC CORPORATION |
发明人 |
ONO TOSHINOBU;TOUMIYA TAMAKI |
分类号 |
G01R31/3183;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/3183 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|