发明名称 Data processor having unified memory architecture providing priority memory access
摘要 In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory is generated from the CPU, the memory controller holds it once, requests the display controller to stop the access to the memory which is in execution, when data to the access executed already is transferred from the memory, holds it, and transfers the access request from the CPU bus which is held by the memory. When the access from the CPU bus ends, the memory controller restarts the access stopped in the display controller and passes the held data to the display controller.
申请公布号 US6333745(B1) 申请公布日期 2001.12.25
申请号 US19970942689 申请日期 1997.09.29
申请人 HITACHI, LTD. 发明人 SHIMOMURA TETSUYA;MATSUO SHIGERU;KATSURA KOYO;INUZUKA TATSUKI;NAKATSUKA YASUHIRO
分类号 G06F13/14;G06F13/16;G06F13/18;G09G1/16;G09G5/00;G09G5/02;G09G5/36;G09G5/39;(IPC1-7):G06F13/16 主分类号 G06F13/14
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