发明名称 |
Semiconductor device using complementary clock and signal input state detection circuit used for the same |
摘要 |
A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.
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申请公布号 |
US6333660(B2) |
申请公布日期 |
2001.12.25 |
申请号 |
US20010780475 |
申请日期 |
2001.02.12 |
申请人 |
FUJITSU LIMITED |
发明人 |
TAGUCHI MASAO;TOMITA HIROYOSHI;MATSUZAKI YASUROU |
分类号 |
G11C7/22;H03K5/00;H03K5/135;H03K5/151;H03L7/081;(IPC1-7):H03K3/013 |
主分类号 |
G11C7/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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