发明名称 METHOD AND APPARATUS FOR INFERRING TEST TIME OF INTEGRATED CIRCUIT DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a method and apparatus for inferring the test time of an integrated circuit device, capable of accurately inferring the test time necessary for testing the quality of the integrated circuit device. SOLUTION: One prescribed test time inferring equation, corresponding to the number of the power supplies connected to the integrated circuit device to be tested, is selected from among a plurality of prescribed test time estimating equations having total number of plural kinds of pins prepared at each number of the power supplies as a variable, and the total number of pins provided to the integrated circuit device to be tested is substituted for the variable of the selected prescribed test time inferring equation to infer the test time of the integrated circuit device.
申请公布号 JP2001343423(A) 申请公布日期 2001.12.14
申请号 JP20000162306 申请日期 2000.05.31
申请人 KAWASAKI STEEL CORP 发明人 KANEKO YOSHIO
分类号 G01R31/28;(IPC1-7):G01R31/28 主分类号 G01R31/28
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