| 摘要 |
PROBLEM TO BE SOLVED: To utilize a memory bandwidth by smoothening memory access. SOLUTION: A CPU 20 stores information to set a line used for vertical filter processing to a setting register 15. An address generator/RAM controller 17 reads a setting value stored in the setting register 15 to recognize a read address of a line used for vertical filter processing and reads image data stored in an SDRAM 11 and stores the data to an FIFO 19 when the FIFO 19 has an idle area. An FIFO controller 16 outputs the image data stored in the FIFO filter 19 in response to a request signal from the vertical filter circuit 13. Thus, it is possible to read the data from the SDRAM 11 in timing not specified by display timing of a line processed by the vertical filter circuit 13 so as to smooth the memory access of the SDRAM 11 thereby utilizing the memory bandwidth.
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