| 摘要 |
<p>A pipeline ADC (100) includes an input stage (12) and a first group of subsequent stages, wherein the input stage includes a unity gain amplifier (16) having an input for receiving an analog input signal, an output, and first and second comparators (17A and 17B) each having a first input coupled to the output of the unity gain amplifier. The first comparator has a second input for receiving a first reference voltage an first output, and the second comparator has a second input for receiving a second reference voltage and an output. The input stage includes a full adder (40A) coupled to the output of the second comparator, and an output producing MSB bit information.</p> |
