| 摘要 |
PROBLEM TO BE SOLVED: To enable a phase comparator to respond quick and discriminate a phase with high precision by eliminating the generation of jitters of a clock signal caused by the phase comparator when the phase comparator is used for, for example, a PLL circuit. SOLUTION: A D-FF 43 detects input data Si with a positive edge of a VCO output signal SO and stores them. The data Si are delayed by a delay circuit 44 by 90 deg. with the phase of the data Si. The data Si and the output signal of the D-FF 44 are exclusively ORed by an EXOR gate 45. Further, the data Si and the output signal of the delay circuit 44 are exclusively ORed by an EXOR gate 46. Consequently, the phase difference between the data Si and VCO output signal So is detected and output signals S47 and S48 which are proportional to the phase difference are outputted. |
