发明名称 SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a CMOS output circuit constituted of a combination of n-stages which can improve surge characteristic. SOLUTION: Surge current input to an N-channel transistor is relaxed and anti-surge characteristic is improved by connecting a metallic output wiring 3 connected to an output pad 2 to a drain d(2n-1)a of a P-channel transistor Q(2n-1) (wherein transistors of the same size as Q1, Q3 are disposed in several stages) and connecting a drain d2na of an N-channel transistor Q2n (wherein transistors of the same size as Q2, Q4 are disposed in several stages) to a post stage thereof as shown in Figure 2. Furthermore, similar effect can be obtained by using a transistor wherein a CMOS output circuit of a final stage is set 'off'. Anti-surge characteristic can be improved by enlarging the distance between back gates bg1, bg2 and a contact 6 of a drain.
申请公布号 JP2001339046(A) 申请公布日期 2001.12.07
申请号 JP20000157492 申请日期 2000.05.29
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TOYAMA TSUTOMU;KOMORI HIROSHI
分类号 H01L27/04;H01L21/82;H01L21/822;H01L21/8238;H01L27/092;(IPC1-7):H01L27/04;H01L21/823 主分类号 H01L27/04
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