| 摘要 |
PURPOSE: A high-quality bit synchronous circuit is provided to embody a high quality by regulating the phase shift of a multi phase clock. CONSTITUTION: A multi phase clock generating circuit(100) generates a plurality of clocks whose phase is crisscrossed with one another in constant interval according to an input clock. A detection circuit(110) detects which clock has a phase shift of integer multiples of one clock period of the input clock from the output generated by the multi phase clock generating unit(100). The multi phase clock generating unit(100) is connected with a plurality of delay circuits which delay the input clock in sequence in constant intervals to generate the multi phase clock. The detection circuit(110) consists of a plurality of D-flipflops.
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