| 摘要 |
<p>A memory [10] that stores a plurality of data storage words, each data storage word includes a plurality of data storage cells [15] arranged as a plurality of columns of data storage cells [15], at least one of the data storage cells [15] storing data specifying a data value having 3 or more states. The memory [10] includes a plurality of data lines, one such data line [13] correspondint to each column of data storage cells [15]. Each data storage cell [15] sets its state or provides a signal representative of its state via the data line [13] connected to that cell in response to control signals. The memory [10] includes an error encryption circuit [11] for receiving a data word to be stored in the memory [10] and generating therefrom an encrypted data storage word. The encryption circuit [11] devides the encrypted data storage word into a plurality of sub-data storage words. An error decrypting circuit [21] generates a corrected data word from the uncorrected sub-data storage words by generating an increment or decrement to be added to an uncorrected sub-data storage word to arrive at a correct sub-data storage word value.</p> |
