发明名称 |
METHOD OF FABRICATION OF AN INTEGRATED CIRCUIT CHIP CONTAINING EEPROM AND CAPACITOR |
摘要 |
An EEPROM cell is formed in an IC chip by using only three masking steps in addition to those required for the basic CMOS transistors in the chip. A first mask layer is used to define source/drain regions of select and memory transistors within the EEPROM cell; a second mask layer is used to define a tunneling region of the memory transistor;and a third mask layer is used to define a floating gate of the memory transistor and a gate of the select transistor. A control gate of the memory transistor is formed using the same mask that is used to define the gates of the CMOS transistors. The third and fourth mask layers may also be used to form the lower and upper electrodes, respectively, of a capacitor. |
申请公布号 |
EP0725980(B1) |
申请公布日期 |
2001.12.05 |
申请号 |
EP19950931647 |
申请日期 |
1995.08.29 |
申请人 |
NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
CACHARELIS, PHILIP, J.;PERRY, JEFFREY, R.;NARAHARI, NARASIMHA |
分类号 |
H01L21/8247;H01L27/06;H01L27/105;(IPC1-7):H01L21/824;H01L27/115 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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