发明名称 Signal latching of high bandwidth DRAM arrays when skew between different components is higher than signal rate
摘要 A system enables the capture of incoming signals from different components when the skew between the different components is higher than the signal rate. The system comprises a first port for serially receiving a first signal at a signal rate from a first component; a second port for serially receiving a second signal at the signal rate from a second component; a first serial-to-parallel conversion circuit for performing serial-to-n-bit-parallel conversion of the first signal, n being greater than one; and a second serial-to-parallel conversion circuit for performing serial-to-n-bit parallel conversion of the second signal.
申请公布号 US6327205(B1) 申请公布日期 2001.12.04
申请号 US20000578354 申请日期 2000.05.24
申请人 JAZIO, INC. 发明人 HAQ EJAZ UL
分类号 H03M9/00;H04L7/00;H04L25/02;H04L25/06;(IPC1-7):G11C7/00;G06F3/00 主分类号 H03M9/00
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