发明名称 |
Pulse width modulation system and image forming apparatus having the pulse width modulation system |
摘要 |
When a CPU begins to monitor whether delay variation characteristics of a pulse width variation circuit have varied, it selects a basic delay setting value in a basic delay value setting block from a smallest one. The CPU sets a division number in a phase select block from a given minimum desired division number for pulse width modulation. The CPU senses the level of a phase comparison result signal (PHASE) from the pulse width modulation circuit. If the phase comparison result signal is stable at "1", the CPU 1 fixes the division number. If the phase comparison result signal is "0" and the division number is not maximum, the CPU increases the division number and goes back to the setting of the division number. If the division number is maximum, the CPU increases the basic delay and goes back to the basic delay setting.
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申请公布号 |
US6326993(B1) |
申请公布日期 |
2001.12.04 |
申请号 |
US20000526289 |
申请日期 |
2000.03.15 |
申请人 |
TOSHIBA TEC KABUSHIKI KAISHA |
发明人 |
SATOH HIROKI;NAKAJIMA MAKOTO;TANIMOTO KOJI |
分类号 |
B41J2/44;G06K15/00;H04N1/405;(IPC1-7):B41J2/47;B41J2/435 |
主分类号 |
B41J2/44 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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