| 摘要 |
<p>PROBLEM TO BE SOLVED: To prevent a hazard from occurring, when switching plural clock signals. SOLUTION: When a source signal SE is switched from '0' to '1', for example, this is detected by a transition detecting means 11, and synchronously with rise of a clock signal CK1, a clock stop control signal ST1 is turned into '1' by a control signal generating means 13. Further, synchronously with rising of a clock signal SK2, a clock stop control signal ST2 is turned into '1' by a control signal generating means 14. The switching time point of the source signal SE from '0' to '1' is delayed by a delay means 12, and after the lapse of several clock pulses from rise of the signals ST1 and ST2 to '1', a select signal SL rises from '0' to '1'. Before and after such a rise, a clock signal CK0 to be outputted from an OR gate 30 is stopped by '1' of the signals ST1 and ST2 and '1' is maintained, so that no hazard will occur in a signal CK0, when switching the signals CK1 and CK2.</p> |
