发明名称 |
MOS TRANSISTOR, MANUFACTURING METHOD THEREOF AND SEMICONDUCTOR DEVICE |
摘要 |
PROBLEM TO BE SOLVED: To enable the operation of a DTMOS as a transistor even if a relatively large voltage is applied to a gate electrode of the DTMOS. SOLUTION: An nDTMOS 50 comprises an nMOS 56 arranged in a first active region 52 composed of p- regions and an nJFET 58 arranged in a second active region 54 composed of n- regions. Furthermore, the nDTMOS 50 is provided with a contact part 62 composed of p+ regions in the first active region 52. The contact part 62 is connected to a gate 64 and a drain 68 of the nJFET 58 through a wiring 78b. A source 66 of the nJFET 58 is connected electrically to a gate electrode 12 of the nMOS 56 through the wiring 78a.
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申请公布号 |
JP2001332702(A) |
申请公布日期 |
2001.11.30 |
申请号 |
JP20000147000 |
申请日期 |
2000.05.18 |
申请人 |
SEIKO EPSON CORP |
发明人 |
MIKOSHIBA KEIMEI |
分类号 |
H01L21/76;H01L21/06;H01L21/337;H01L21/8232;H01L21/8234;H01L27/06;H01L27/08;H01L29/786;H01L29/808;(IPC1-7):H01L27/08;H01L21/823 |
主分类号 |
H01L21/76 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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