| 摘要 |
A PLL circuit includes a phase comparator which makes a comparison between an internal clock signal and a clock signal supplied from an external terminal, a charge pump circuit which produces a charging-up or discharging current in accordance with the output of the phase comparator, so as to drive a filter capacitor, a voltage-controlled oscillator the oscillation frequency of which is controlled by the held voltage of the filter capacitor, and a frequency divider circuit which generates the internal clock signal on the basis of the oscillation output of the voltage-controlled oscillator. The PLL circuit is additionally provided with a voltage detector circuit which detects that the held voltage of the filter capacitor has been raised to a predetermined voltage or higher, and the function of forcedly lowering the held voltage of the filter capacitor down to a predetermined potential in accordance with the detection output of the voltage detector circuit. Besides, a system is provided with a detection and setting circuit which detects a state brought about by the electrical disconnection of the feedback loop of the PLL circuit, and which brings the PLL circuit into a predetermined state.
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