发明名称 |
Phase comparator and clock recovery circuit |
摘要 |
<p>A phase comparator in a PLL comprises a phase comparing portion (17) having inputs for data (6) and clock (5) signals and generates leading (U4) and lagging (D4a) pulses to be supplied to a charge pump. A correcting pulse generation portion (18) generates a correction pulse from the input clock and data signals. A resetting portion (19) is supplied with the correction pulse, the clock signal and the leading and lagging pulses and generates a reset pulse to reset the phase comparator portion. The correction pulse is also supplied to a pulse correcting portion (20) to remove false pulses contained in the incomplete lagging pulse train. <IMAGE></p> |
申请公布号 |
EP1158680(A1) |
申请公布日期 |
2001.11.28 |
申请号 |
EP20010111939 |
申请日期 |
2001.05.18 |
申请人 |
YAZAKI CORPORATION |
发明人 |
IDEI, GIJUN;UNNO, KAZUYOSHI |
分类号 |
H03D13/00;H03L7/089;H04L7/033;(IPC1-7):H03L7/089 |
主分类号 |
H03D13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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