Improvements in shift registers using single type MIS transistors

摘要

The first transistor (MN2) is controlled by the potential at a second node (G). This node is connected to the output from the previous stage (n-1) which is across a second transistor (MN1), controlled by the previous stage and a negative potential (V-) across a third transistor (MN3) which is controlled by the output of the next stage (n+1). Another second clock signal ( 2) is provided across a first capacitance (C2) and a capacitance (C3) lies between the second node and the output of the next stage. Another negative voltage (Vgoff) is connected to the output across a fourth transistor (MN4) which is controlled by the output of the following or the next but one stage.