| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit realizing the stability and a high speed operation of the read-out system of an EEPROM. SOLUTION: This circuit has a sense amplifier 3, an operation amplifier OP, and current source load PMOSs QP1, QP2. A sense node SA is connected to a selected bit line BL in a memory cell array 1 through a NMOS transistor QN1 for clamp and a column 2. A reference node REF is connected to a reference cell PMC through a NMOS transistor QN2 for dummy clamp and a dummy column gate QN3. A bias circuit 5 driving the NMOS transistors QN1, QN2 for clamp is constituted of a BGR circuit 51 and a regulator 52 multiplying proportionally its output reference voltage Vref.</p> |
