| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory which can be operated at a high speed by reducing the load on a data line. SOLUTION: A memory cell array block 202 outputs a data signal of a memory cell through an I/O line 216. I/O line sense amplifiers 208 provided for every I/O line 216 amplify a data signal and output it. A data line sense amplifier 210 connected to respective I/O line sense amplifier 208 simplify a data signal more and output it. A data line pre-charge circuit 212 precharges a data line 218 to the prescribe voltage level before a data signal is outputted from the data line sense amplifier 210, when a data signal is outputted, a data signal shifted to a high level or a low level transited is outputted in accordance with a logic level of the data signal.
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