| 摘要 |
A delay verification device includes a circuit information storing unit for storing circuit information of a logic circuit, a before layout designing delay information storing unit for storing before layout designing delay information on a delay time between circuit elements predicted before layout designing, an after layout designing delay information storing unit for storing after layout designing delay information on a delay time between circuit elements computed after layout designing of the logic circuit, a difference extracting unit for comparing the before layout designing delay information and the after layout designing delay information to extract and register difference information on a portion of the logic circuit, whose delay time of the after layout designing delay information is longer than that of the before layout designing delay information, a tracing unit for searching paths of the logic circuit to extract a path including a portion of the logic circuit corresponding to the difference information, an extracted circuit information storing unit for storing an extracted circuit information, and a delay analyzing unit for analyzing delays of the logic circuit based on the extracted circuit information and the after layout designing delay information.
|
